集聚多种优势:Freescale QE128血压计参考设计方案

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    *  QE128血压计参考设计方案

Freescale公司的血压计(BPM)参考设计采用MC9S08QE128作为微控制器,具有控制,数据保持,模拟采集和连接功能以及能和用户接口. 参考设计具有多种优势:采用MC9S08JM60作为USB通信的桥,采用MC13202 ZigBee收发器进行2.4GHz通信,采用MRAM来存储用户数据和通信,MRAM驱动器能存取MRAM存储器,采用OLED作为用户显示, MPR083接近式传感器用作用户接口,以及用两个定时PWM模块作为音频反馈.本文首先介绍了MC9S08QE128主要特性和方框图.接着介绍了血压计(BPM)参考设计的硬件方框图和软件架构流程图,以及详细电路图和所用材料清单.

MC9S08QE128主要特性:

• 8-Bit HCS08 Central Processor Unit (CPU)

– Up to 50.33-MHz HCS08 CPU above 2.4V, 40-MHz CPU above 2.1V, and 20-MHz CPU above 1.8V, across temperature range

– HC08 instruction set with added BGND instruction

– Support for up to 32 interrupt/reset sources

• On-Chip Memory

– Flash read/program/erase over full operating voltage and temperature

– Random-access memory (RAM)

– Security circuitry to prevent unauthorized access to RAM and flash contents

• Power-Saving Modes

– Two low power stop modes; reduced power wait mode

– Peripheral clock enable register can disable clocks to unused modules, reducing currents; allows clocks to remain enabled to specific peripherals in stop3 mode

– Very low power external oscillator can be used in stop3 mode to provide accurate clock to active peripherals

– Very low power real time counter for use in run, wait, and stop modes with internal and external clock sources

– 6 μs typical wake up time from stop modes

• Clock Source Options

– Oscillator (XOSC) — Loop-control Pierce oscillator; Crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz

– Internal Clock Source (ICS) — FLL controlled by internal or external reference; precision trimming of internal reference allows 0.2% resolution and 2% deviation; supports CPU freq. from 2 to 50.33 MHz

• System Protection

– Watchdog computer operating properly (COP) reset with option to run from dedicated 1-kHz internal clock source or bus clock

– Low-voltage detection with reset or interrupt; selectable trip points

– Illegal opcode detection with reset

– Flash block protection

• Development Support

– Single-wire background debug interface

– Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints)

– On-chip in-circuit emulator (ICE) debug module containing two comparators and nine trigger modes. Eight deep FIFO for storing change-of-flow addresses and event-only data. Debug module supports both tag and force breakpoints.

• ADC — 24-channel, 12-bit resolution; 2.5 μs conversion time; automatic compare function; 1.7 mV/°C temperature sensor; internal bandgap reference channel; operation in stop3; fully functional from 3.6V to 1.8V
 

• ACMPx — Two analog comparators with selectable interrupt on rising, falling, or either edge of comparator output; compare option to fixed internal bandgap reference voltage; outputs can be optionally routed to TPM module; operation in stop3

• SCIx — Two SCIs with full duplex non-return to zero (NRZ); LIN master extended break generation; LIN slave extended break detection; wake up on active edge

• SPIx— Two serial peripheral interfaces with Full-duplex or single-wire bidirectional; Double-buffered transmit and receive; MSB-first or LSB-first shifting

• IICx — Two IICs with; Up to 100 kbps with maximum bus loading; Multi-master operation; Programmable slave address; Interrupt driven byte-by-byte data transfer; supports broadcast mode and 10 bit addressing

• TPMx — One 6-channel and two 3-channel; Selectable input capture, output compare, or buffered edge- or center-aligned PWMs on each channel

• RTC — 8-bit modulus counter with binary or decimal based prescaler; External clock source for precise time base, time-of-day, calendar or task scheduling functions; Free running on-chip low power oscillator (1 kHz) for cyclic wake-up without external components

• Input/Output

– 70 GPIOs and 1 input-only and 1 output-only pin

– 16 KBI interrupts with selectable polarity

– Hysteresis and configurable pull-up device on all input pins; Configurable slew rate and drive strength on all output pins.

– SET/CLR registers on 16 pins (PTC and PTE)

图1.MC9S08QE128系列方框图

采用QE128系列的血压计参考设计

Blood Pressure Monitor Using the Flexis QE128 Family

The blood pressure monitor (BPM) reference design shows how to implement a system that can measure arterial blood pressure values. The system demonstrates control, data retention, analog acquisition, and connectivity functions, as well as the ability to interface with a user. These are achieved by using several Freescale devices.

This reference design serves only as a proof of concept for this application and is not authorized for use in safety-critical applications such as a U.S. Food and Drug Administration (FDA) class 3 application.

Manufacturers and designers who incorporate Freescale (FSL) technology must have all necessary expertise in the safety and regulatory ramifications involved in the application of this design, and they are solely responsible for all legal, regulatory, and safety-related requirements concerning their products and the use of Freescale devices in safety-critical applications.
 

采用QE128系列的血压计参考设计优势

The BPM reference design elements can be referenced for later development as:

• USB communication using the MC9S08JM60 as a bridge

• 2.4 GHz communication using the MC13202 ZigBee transceiver

• MRAM communications

• Use of MRAM to store user data

• MRAM driver to access MRAM memory

• User display using an OLED display

• User interface using the MPR083 proximity sensor

• Audio feedback using two timer pulse-width modulator (TPM) modules

The main benefit from this solution is that developers are able to take any piece of hardware and/or software and reuse it for their own applications, thus enhancing the design cycle and providing faster development time.

图2.Flexis BPM 参考设计方框图

图3.血压计软件架构流程图
 

图4.血压计参考设计电路图(1)

图5.血压计参考设计电路图(2)

图6.血压计参考设计电路图(3)

图7.血压计参考设计电路图(4)
 

图8.血压计参考设计电路图(5)

图9.血压计参考设计电路图(6)

图10.血压计参考设计电路图(7)
 

图11.血压计参考设计电路图(8)

图12.血压计参考设计电路图(9)

图13.血压计参考设计电路图(10)

图14.血压计参考设计电路图(11)
 

血压计参考设计材料清单(BOM):